3 to 8 decoder using 2 to 4 decoder verilog code

3 to 8 decoder using 2 to 4 decoder verilog code


  • Designing of 3 Line to 8 Line Decoder and Demultiplexer
  • Combinational circuits using Decoder
  • Verilog Code: Decoder (3:8) using if-else
  • Verilog Programming Series – 2 to 4 Decoder
  • External memory interfacing in 8085: RAM and ROM
  • Types of Binary Decoders,Applications
  • VHDL Code for 2 to 4 decoder
  • Designing of 3 Line to 8 Line Decoder and Demultiplexer

    The final circuit Memory support in An microprocessor has a bit address bus. Each bit can take the value of either 0 or 1. So, the total number of addresses that can be generated on a bit address bus will be And each unique address refers to a memory block containing 8 bits or 1 byte of space. Thus, we can say that can support a memory chip of size up to 64 kB. We can interface a memory chip of size less than that too.

    Also, we can interface several memory chips to a single microprocessor, until and unless their combined size does not exceed 64 kB. Let us learn how to achieve all that. Memory chips of different types and sizes Memory chips come in a variety of types and with different storage capacities. A broad classification of memory chips based on their read and write capability is: RAM Random Access Memory : We can read as well as write data on this type of memory.

    The chip of this type has pins for both memory read and memory write signals. The chip of this type has a pin only for memory read signal. Now, you must be wondering what does a microprocessor read from a ROM if data cannot be written on it. Data cannot be written on it by a microprocessor when it is connected in the circuit. But data can be written on it using some special techniques.

    This kind of memory is used to store programs, while RAM is used to store the data. Data is written on it optically. You can learn more about all the types of digital memories here. Memory chips come in different sizes. The illustration shows below what these numbers in the specification of a memory chip capacity size mean. Let us take up a problem regarding the interfacing of memory and solve it as we learn the topic. You can assign the address range of your choice to the 2 kB RAM.

    The first step to solve this problem is to understand the pins of the given memory chips. Let us understand the pins one by one. Data pins: Since each memory location stores eight bits, there are eight data lines D0-D7 connected to the memory chip. Address pins: The number of address pins depends on the size of the memory. In this case, a memory of size 1 kB x 8 will have different memory locations.

    Hence, it will have ten address lines A0 to A9. Similarly, the 2 kB RAM will have different memory locations. So, there are 11 address lines A0-A CS pin: When this pin is enabled, the memory chip knows that the microprocessor is talking to it and responds to it accordingly.

    We need to generate this signal for each of the chips according to the range of addresses assigned to them. Basically, we select a chip only when it is needed. The Chip Select CS pin is used for this. OE pin: When this active-low output enable pin is enabled, the memory chip can output the data into the data bus. WR pin: Upon activation of this active-low memory write pin, data on the data bus is written on the memory chip at the location specified by the address bus. For simplicity, we will not show these pins in the diagram.

    There are three types of buses in — Address bus, data bus, and control bus. Each of these buses will be connected to the memory chip. These will be connected to the control signals generated using a 3 to 8 decoder. To read about the generation of control signals, you can read our post on Demultiplexing of Bus and Generating Control Signals. The circuit for generating control signals is shown below.

    After completing these two connections, we are done with the control signals except CS. We will deal with that in a bit. Data Bus interfacing There are eight lines comprising the data bus of both and the memory chips. The interfacing of the data bus is the simplest part. We just connect corresponding lines D0-D7 from to the corresponding pins D0-D7 of the memory chip.

    So, the first 11 lines of the address bus of will be connected to the corresponding address lines of the 2kB RAM. The remaining address lines will be used to generate the chip select CS signal. Let us proceed step by step and build up an intuition of how to generate the chip select signal for a memory of given size and given address range. A15 is most significant, and A0 is the least significant bit.

    Combinational circuits using Decoder

    Instruction Decoder Binary Decoders A binary decoder is a multi-input, multi-output combinational circuit that converts a binary code of n input lines into a one out of 2n output code. These are used when there is need to activate exactly one of 2n output based on an n-bit input value. The figure below shows the general structure of binary decoder in which encoded information is accepted at n input lines and the output is produced at 2n possible output lines.

    Generally, decoders are provided with enable inputs so as to activate the decoded output based on data inputs. As an example, in case of BCD code, the 4 bit combinations from through are enough to represent the decimal digits 0 to 9. Depending on the number of input lines, the inputs of a binary code can be 2-bit or 3-bit or 4-bit codes. Upon the availability of 2n lines, it activates the one of its output by deactivating making logic 0 all other input whenever it receives n inputs.

    Usually the number of bits in output code is more than the bits in its input code. The most commonly used practical binary decoders are 2-to-4 decoder, 3-to-8 decoder and 4-to line binary decoder.

    Only one output is active at any time while the other outputs are maintained at logic 0 and the output which is held active or high is determined the two binary inputs A and B. The figure below shows the truth table for a 2-to-4 decoder. When both the inputs are high, then the output Y3 will be high.

    If the enable bit is zero then all the outputs will be set to zero. This relationship between the inputs and outputs are illustrated in below truth table clearly. From the above truth table we can obtain Boolean expression for the each output as These expressions can be implemented by using basic logic gates. Thus, the logic circuit design of the 2-to-4 line decoder is given below which is implemented by using NOT and AND gates.

    Two NOT gates or inverters provide the complement of inputs. Each output represents one of the minterms of the 2 input variables. It is also possible to design 2-to-4 decoder using NAND gates as shown in figure below along with truth table. This is constructed with a principle of max terms as outputs. To generate the minterms, we have to use NAND gates which act as inverters. Therefore, only one output will be low for any combinations of inputs at a given time and all other outputs will be high.

    This type of decoders is available in IC forms so that 3 to 8, 4 to 16, and 5 to 32 decoders can also be made depends on the application requirement. Based on the combinations of the three inputs, only one of the eight outputs is selected. The figure below shows the truth table of a 3-to-8 decoder. Enable input is provided to activate the decoded output depends on the input combinations A, B and C. So from the truth table, minterms represents the each output equation and are given as Using the above min term expressions for each output, the circuit of 3-to-8 decoder is can be implemented by using three NOT gates and eight AND gates.

    Also enable input activate the decoded output depends on the input data. The logic diagram of this decoder is shown below. Only one of eight outputs is high at a given time for a particular input combination, that why this decoder is also called as 1-of-8 decoder. In such case, inversion operation is performed in the logic circuit than that of circuit with min terms. The figure below shows the truth table of 3-to-8 line decoder using NAND gates.

    Each output in the table gives a max term representation. At a given time only one output is low and all other outputs will be high. NOT gates generate the complement of input while the NAND gates generate max terms of each output as shown in below figure. Similar to all the decoders discussed above, in this also only one output will be low at a given time and all other outputs are high using maxterms.

    The truth table of this type of decoder is shown below. If the input to this decoder is , then output Y8 will be low and all other outputs will be high as shown in figure. This will be so on for all the input combinations. It is important to note that all the NAND gates are implemented on this circuit produce the active low outputs as shown in figure. Since it selects one of 16 outputs based in the particular input combination, these decoders are also called as 1-of decoder.

    And also its output represents the sixteen digits as hexadecimal number system, this type of decoder is also called as a binary-to-hexadecimal decoder. It is possible to combine or cascade two or more decoders to produce a decoder with larger number of input bits with the use of enable input of decoder. The cascade combination of two 3-to-8 line decoder is given below figure.

    One of the input variable is used as enable input of the first 3-to-4 decoder and this same input is complemented and connected as enable input of the second decoder.

    The decoder to be enabled is decided by the most significant input variable and other input variables are fed to each decoder.

    When enable input is zero then the top decoder is enabled while the other is disabled. Then the top decoder eight outputs generate the minterms to Likewise, when enable is 1, the lower decoder is enabled and top one is disabled.

    Thus the bottom decoder outputs generate minterms from to Applications of Decoders Decoders are greatly used in applications where the particular output or group of outputs to be activated only on the occurrence of a specific combination of input levels. Very often these input levels are provided by the outputs of a register or counter.

    When the counter or register continuously pulse the decoder inputs, the outputs will be activated sequentially. And these outputs can be used as sequencing signals or timing signals to switch the devices at particular times. Binary to Decimal Decoder Decoders are used to get the decimal digit corresponding to a specific input combination.

    A BCD number needs 4 binary digits to represent the 0 to 9 decimal digits, thus it consists of 4 input lines. It consists of 10 output lines corresponding to 0 to 9 decimal digits. T This type of decoder is also called as a 1 to 10 decoder.

    For a specific input combination, the output will be activated corresponding to the decimal equivalent of the input combination. Address Decoders Amongst its many uses, a decoder is widely used to decode the particular memory location in the computer memory system. Decoders accept the address code generated by the CPU which is a combination of address bits for a specific location in the memory.

    In a memory system, there are several memory ICs are combined and each one has their unique address to distinguish from other memory locations. In such cases a decoder built in the memory ICs circuitry, is used to select a memory IC in response to a range of addresses by decoding the most significant bits of the systems address, thereby a particular memory location or IC is selected. In a more complex memory system, the memory ICs or chips are arranged in multiple banks.

    When the microprocessor wants to access one or more bytes at a time, these banks must be selected simultaneously or individually. In such cases more than one decoder must be activated. For that, cascaded decoders are used or most commonly decoders are replaced with programmable logic devices.

    Instruction Decoder Another application of the decoder can be found in the control unit of the central processing unit. This decoder is used to decode the program instructions in order to activate the specific control lines such that different operations in the ALU of the CPU are carried out. Related Posts:.

    Verilog Code: Decoder (3:8) using if-else

    Instruction Decoder Binary Decoders A binary decoder is a multi-input, multi-output combinational circuit that converts a binary code of n input lines into a one out of 2n output code.

    These are used when there is need to activate exactly one of 2n output based on an n-bit input value. The figure below shows the general structure of binary decoder in which encoded information is accepted at n input lines and the output is produced at 2n possible output lines. Generally, decoders are provided with enable inputs so as to activate the decoded output based on data inputs. As an example, in case of BCD code, the 4 bit combinations from through are enough to represent the decimal digits 0 to 9.

    Depending on the number of input lines, the inputs of a binary code can be 2-bit or 3-bit or 4-bit codes.

    Verilog Programming Series – 2 to 4 Decoder

    Upon the availability of 2n lines, it activates the one of its output by deactivating making logic 0 all other input whenever it receives n inputs. Usually the number of bits in output code is more than the bits in its input code. The most commonly used practical binary decoders are 2-to-4 decoder, 3-to-8 decoder and 4-to line binary decoder. Only one output is active at any time while the other outputs are maintained at logic 0 and the output which is held active or high is determined the two binary inputs A and B.

    The figure below shows the truth table for a 2-to-4 decoder. When both the inputs are high, then the output Y3 will be high.

    External memory interfacing in 8085: RAM and ROM

    If the enable bit is zero then all the outputs will be set to zero. This relationship between the inputs and outputs are illustrated in below truth table clearly. From the above truth table we can obtain Boolean expression for the each output as These expressions can be implemented by using basic logic gates.

    Thus, the logic circuit design of the 2-to-4 line decoder is given below which is implemented by using NOT and AND gates.

    Two NOT gates or inverters provide the complement of inputs.

    Types of Binary Decoders,Applications

    Each output represents one of the minterms of the 2 input variables. It is also possible to design 2-to-4 decoder using NAND gates as shown in figure below along with truth table.

    This is constructed with a principle of max terms as outputs. To generate the minterms, we have to use NAND gates which act as inverters.

    Therefore, only one output will be low for any combinations of inputs at a given time and all other outputs will be high. This type of decoders is available in IC forms so that 3 to 8, 4 to 16, and 5 to 32 decoders can also be made depends on the application requirement. The below is the truth table for a simple 1 to 2 line decoder where A is the input and D0 and D1 are the outputs.

    A demultiplexer takes one single input data and then selects any one of the single output lines one at a time. It is the reverse process of a multiplexer.

    A decoder is used to select among many devices whereas a demultiplexer is used to send the signal to many devices. The main function of a decoder is to change a code into a set of signals because it is opposite to an encoder, but the designing decoders is simple. The main difference between a decoder and a demultiplexer is a combinational circuit that is used to allow only one input as well as direct it into one of the outputs, whereas a decoder allows several inputs and generates the decoded output.

    Before going to implement this decoder we have designed a 2 line to 4 line decoder. The block diagram of this decoder is shown below. But data can be written on it using some special techniques.

    This kind of memory is used to store programs, while RAM is used to store the data. Data is written on it optically. You can learn more about all the types of digital memories here.

    Memory chips come in different sizes.

    VHDL Code for 2 to 4 decoder

    The illustration shows below what these numbers in the specification of a memory chip capacity size mean. Let us take up a problem regarding the interfacing of memory and solve it as we learn the topic. You can assign the address range of your choice to the 2 kB RAM. The first step to solve this problem is to understand the pins of the given memory chips.

    Let us understand the pins one by one. Data pins: Since each memory location stores eight bits, there are eight data lines D0-D7 connected to the memory chip. Address pins: The number of address pins depends on the size of the memory. In this case, a memory of size 1 kB x 8 will have different memory locations. Hence, it will have ten address lines A0 to A9. Similarly, the 2 kB RAM will have different memory locations.

    So, there are 11 address lines A0-A CS pin: When this pin is enabled, the memory chip knows that the microprocessor is talking to it and responds to it accordingly.


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